vampirefrog 1 year ago
parent
commit
fad258a042
3 changed files with 142 additions and 25 deletions
  1. 76
    25
      v68.c
  2. 56
    0
      v68ipl.c
  3. 10
    0
      v68ipl.h

+ 76
- 25
v68.c View File

@@ -29,6 +29,7 @@ int v68_init(int clock, int ram_size, int sample_rate) {
29 29
 	m68k_set_cpu_type(M68K_CPU_TYPE_68000);
30 30
 	m68k_pulse_reset();
31 31
 
32
+	v68_ipl_init();
32 33
 	v68_periph_init();
33 34
 	v68_io_init();
34 35
 	v68_human_init();
@@ -82,45 +83,89 @@ int v68_fill_buffer(int16_t *bufL, int16_t *bufR, int samples) {
82 83
 }
83 84
 
84 85
 unsigned int m68k_read_memory_8(unsigned int addr) {
85
-	if(addr >= 0x00e80000 && addr < 0x00eb0000)
86
-		return v68_read_periph_8(addr);
87
-	else if(addr > v68.ram_size) {
88
-		verbose2("Could not read RAM at 0x%08x\n", addr);
86
+	// addr &= 0x00ffffff;
87
+
88
+	if(addr >= 0x00fe0000 && addr <= 0x00ffffff) {
89
+		uint8_t r = v68_ipl_read_8(addr);
90
+		verbose3("READ8 IPL 0x%08x = 0x%02x\n", addr, r);
91
+		return r;
92
+	}
93
+
94
+	if(addr >= 0x00e80000 && addr < 0x00eb0000) {
95
+		uint8_t r = v68_read_periph_8(addr);
96
+		verbose3("READ8 PERIPH 0x%08x = 0x%02x\n", addr, r);
97
+		return r;
98
+	}
99
+
100
+	if(addr >= v68.ram_size) {
101
+		verbose2("READ8 ERROR 0x%08x\n", addr);
89 102
 		return 0;
90 103
 	}
91
-	unsigned int i = v68.ram[addr];
92
-	verbose3("READ8  @0x%08x = 0x%02x\n", addr, i);
93
-	return i;
104
+
105
+	uint8_t r = v68.ram[addr];
106
+	verbose3("READ8 RAM 0x%08x = 0x%02x\n", addr, r);
107
+	return r;
94 108
 }
95 109
 
96 110
 unsigned int  m68k_read_memory_16(unsigned int addr) {
97
-	if(addr >= 0x00e80000 && addr < 0x00eb0000) return v68_read_periph_16(addr);
98
-	else if(addr > v68.ram_size) {
99
-		verbose2("Could not read RAM at 0x%08x\n", addr);
111
+	// addr &= 0x00ffffff;
112
+
113
+	if(addr >= 0x00fe0000 && addr <= 0x00ffffff) {
114
+		uint16_t r = v68_ipl_read_16(addr);
115
+		verbose3("READ16 IPL 0x%08x = 0x%04x\n", addr, r);
116
+		return r;
117
+	}
118
+
119
+	if(addr >= 0x00e80000 && addr < 0x00eb0000) {
120
+		uint16_t r = v68_read_periph_16(addr);
121
+		verbose3("READ16 PERIPH 0x%08x = 0x%04x\n", addr, r);
122
+		return r;
123
+	}
124
+
125
+	if(addr >= v68.ram_size - 1) {
126
+		verbose2("READ16 ERROR 0x%08x\n", addr);
100 127
 		return 0;
101 128
 	}
102
-	unsigned int i = (v68.ram[addr] << 8) | v68.ram[addr + 1];
103
-	verbose3("READ16 @0x%08x = 0x%04x\n", addr, i);
104
-	return i;
129
+
130
+	uint16_t r = (v68.ram[addr] << 8) | v68.ram[addr + 1];
131
+	verbose3("READ16 RAM 0x%08x = 0x%04x\n", addr, r);
132
+	return r;
105 133
 }
106 134
 
107 135
 unsigned int  m68k_read_memory_32(unsigned int addr) {
108
-	if(addr >= 0x00e80000 && addr < 0x00eb0000) return v68_read_periph_32(addr);
109
-	else if(addr > v68.ram_size) {
110
-		verbose2("Could not read RAM at 0x%08x\n", addr);
136
+	// addr &= 0x00ffffff;
137
+
138
+	if(addr >= 0x00fe0000 && addr <= 0x00ffffff) {
139
+		uint32_t r = v68_ipl_read_32(addr);
140
+		verbose3("READ32 IPL 0x%08x = 0x%08x\n", addr, r);
141
+		return r;
142
+	}
143
+
144
+	if(addr >= 0x00e80000 && addr < 0x00eb0000) {
145
+		uint32_t r = v68_read_periph_32(addr);
146
+		verbose3("READ32 PERIPH 0x%08x = 0x%08x\n", addr, r);
147
+		return r;
148
+	}
149
+
150
+	if(addr > v68.ram_size) {
151
+		verbose2("READ32 ERROR 0x%08x\n", addr);
111 152
 		return 0;
112 153
 	}
113
-	unsigned int i = (v68.ram[addr] << 24) | (v68.ram[addr+1] << 16) | (v68.ram[addr+2] << 8) | v68.ram[addr+3];
114
-	verbose3("READ32 @0x%08x = 0x%08x\n", addr, i);
115
-	return i;
154
+
155
+	uint32_t r = (v68.ram[addr] << 24) | (v68.ram[addr+1] << 16) | (v68.ram[addr+2] << 8) | v68.ram[addr+3];
156
+	verbose3("READ32 @0x%08x = 0x%08x\n", addr, r);
157
+	return r;
116 158
 }
117 159
 
118 160
 void m68k_write_memory_8(unsigned int addr, unsigned int data) {
119
-	verbose3("WRITE8  @0x%08x = %02x\n", addr, data);
161
+	// addr &= 0x00ffffff;
162
+
163
+	verbose3("WRITE8 0x%08x = %02x\n", addr, data);
120 164
 	if(addr >= 0x00e80000 && addr < 0x00eb0000) {
121 165
 		v68_write_periph_8(addr, data);
122 166
 		return;
123
-	} else if(addr > v68.ram_size) {
167
+	}
168
+	if(addr > v68.ram_size) {
124 169
 		verbose2("Could not write RAM at 0x%08x = 0x%02x\n", addr, data);
125 170
 		return;
126 171
 	}
@@ -128,11 +173,14 @@ void m68k_write_memory_8(unsigned int addr, unsigned int data) {
128 173
 }
129 174
 
130 175
 void m68k_write_memory_16(unsigned int addr, unsigned int data) {
131
-	verbose3("WRITE16 @0x%08x = %04x\n", addr, data);
176
+	// addr &= 0x00ffffff;
177
+
178
+	verbose3("WRITE16 0x%08x = %04x\n", addr, data);
132 179
 	if(addr >= 0x00e80000 && addr < 0x00eb0000) {
133 180
 		v68_write_periph_16(addr, data);
134 181
 		return;
135
-	} else if(addr > v68.ram_size) {
182
+	}
183
+	if(addr > v68.ram_size) {
136 184
 		verbose2("Could not write RAM at 0x%08x = 0x%04x\n", addr, data);
137 185
 		return;
138 186
 	}
@@ -141,11 +189,14 @@ void m68k_write_memory_16(unsigned int addr, unsigned int data) {
141 189
 }
142 190
 
143 191
 void m68k_write_memory_32(unsigned int addr, unsigned int data) {
144
-	verbose3("WRITE32 @0x%08x = %08x\n", addr, data);
192
+	// addr &= 0x00ffffff;
193
+
194
+	verbose3("WRITE32 0x%08x = %08x\n", addr, data);
145 195
 	if(addr >= 0x00e80000 && addr < 0x00eb0000) {
146 196
 		v68_write_periph_32(addr, data);
147 197
 		return;
148
-	} else if(addr > v68.ram_size) {
198
+	}
199
+	if(addr > v68.ram_size) {
149 200
 		verbose2("Could not write RAM at 0x%08x = 0x%08x\n", addr, data);
150 201
 		return;
151 202
 	}

+ 56
- 0
v68ipl.c View File

@@ -0,0 +1,56 @@
1
+#include <stdint.h>
2
+#include "v68ipl.h"
3
+#include "v68.h"
4
+
5
+uint8_t iplrom[IPL_ROM_SIZE];
6
+
7
+static void write_ipl_16(uint32_t addr, const uint16_t *data, int data_len) {
8
+	uint8_t *p = iplrom + addr - IPL_ROM_START;
9
+	const uint16_t *d = data;
10
+	for(int i = 0; i < data_len; i++) {
11
+		*p++ = *d >> 8;
12
+		*p++ = *d & 0xff;
13
+		d++;
14
+	}
15
+}
16
+
17
+void v68_ipl_init() {
18
+#define DMA3_VEC_END 0x6a
19
+#define DMA3_VEC_ERR 0x6b
20
+#define DMA3_INT_ADDR 0xff1940
21
+	const uint16_t dma3_int[] = {
22
+		/* DMA 3 interrupt handler */
23
+		0x2f08,                         /* move.l a0, -(a7)           */
24
+		0x41f9, 0x00e8, 0x40c0,         /* lea.l ($00e840c0), a0      */
25
+		0x11e8, 0x0001, 0x0c33,         /* move.b ($0001,A0), ($0c33) */
26
+		0x4a38, 0x0c32,                 /* tst.b ($0c32)              */
27
+		0x6b18,                         /* bmi.b ($00FF196C)          */
28
+		0x13fc, 0x0001, 0x00e9, 0xa007, /* move.b #$01, ($00e9a007)   */
29
+		0x13fc, 0x0003, 0x00e9, 0xa007, /* move.b #$03, ($00e9a007)   */
30
+		0x13fc, 0x0001, 0x00e9, 0x2001, /* move.b #$01, ($00e92001)   */
31
+		0x4a10,                         /* tst.b (a0)                 */
32
+		0x50d0,                         /* st (a0)                    */
33
+		0x4238, 0x0c32,                 /* clr.b ($0c32)              */
34
+		0x205f,                         /* movea.l (a7)+, a0          */
35
+		0x4e73,                         /* rte                        */
36
+	};
37
+
38
+	write_ipl_16(DMA3_INT_ADDR, dma3_int, sizeof(dma3_int) / sizeof(dma3_int[0]));
39
+	m68k_write_memory_32(DMA3_VEC_END * 4, DMA3_INT_ADDR);
40
+	m68k_write_memory_32(DMA3_VEC_ERR * 4, DMA3_INT_ADDR);
41
+}
42
+
43
+uint8_t v68_ipl_read_8(uint32_t addr) {
44
+	addr -= 0xfe0000;
45
+	return iplrom[addr];
46
+}
47
+
48
+uint16_t v68_ipl_read_16(uint32_t addr) {
49
+	addr -= 0xfe0000;
50
+	return (iplrom[addr] << 8) | iplrom[addr + 1];
51
+}
52
+
53
+uint32_t v68_ipl_read_32(uint32_t addr) {
54
+	addr -= 0xfe0000;
55
+	return (iplrom[addr] << 24) | (iplrom[addr + 1] << 16) | (iplrom[addr + 2] << 8) | iplrom[addr + 3];
56
+}

+ 10
- 0
v68ipl.h View File

@@ -0,0 +1,10 @@
1
+#pragma once
2
+
3
+#define IPL_ROM_START 0xfe0000
4
+#define IPL_ROM_SIZE 128 * 1024 /* 128kB */
5
+extern uint8_t iplrom[IPL_ROM_SIZE];
6
+
7
+void v68_ipl_init(void);
8
+uint8_t v68_ipl_read_8(uint32_t addr);
9
+uint16_t v68_ipl_read_16(uint32_t addr);
10
+uint32_t v68_ipl_read_32(uint32_t addr);

Loading…
Cancel
Save